1. Field of the Invention
This invention relates to a chip-supporting substrate for semiconductor packaging, a semiconductor package, and a process for fabricating the semiconductor package.
2.Description of the Related Art
The number of input/output terminals has increased with improvements in the integration of semiconductors. Accordingly, it has become necessary to provide a semiconductor package having a large number of input/output terminals. In general, the input/output terminals are grouped into a type in which they are arranged around a package in a row and a type in which they are arranged in multiple rows not only around but also inside the package. The former is typified by QFP (quad flat package). When this is made to have a larger number of terminals, terminal pitches must be made smaller, where, in a region of 0.5 mm pitch or less, a high-level technique is required to connect them to the wiring board. The latter array type enables the terminals to be arranged at a relatively large pitch, and hence this is suited for providing multiple pins. Conventionally, PGA (pin grid array) having connecting pins is commonly used as the array type, but this is not suitable for surface packaging because the terminals are connected to the wiring board by insertion. Thus, a package called BGA (ball grid array) has been developed, which enables the surface mounting.
Meanwhile, with the miniaturization of electronic equipment, there is an increasing demand for making the package size much smaller. As a measure to cope with such a demand for smaller size, what is called the chip size package (CSP) has been proposed, which has substantially the same size as a semiconductor chip. This is a package having the connections to an external wiring substrate not around the semiconductor chip but in the mounting region. As examples thereof, it includes a package prepared by bonding a polyimide film having bumps to the surface of a semiconductor chip and providing electrical connections to the chip through gold lead wires, followed by potting with epoxy resin or the like to effect sealing (NIKKEI MATERIALS & TECHNOLOGY 94.4, No. 140, pp.18-19), and a package prepared by forming metal bumps on a provisional substrate at its positions corresponding to the connections to a semiconductor chip and an external wiring substrate and attaching the semiconductor chip by face-down bonding, followed by transfer molding on the provisional substrate ("Smallest Flip-chip-like Package CSP", The Second VLSI Packaging Workshop of Japan, pp.46-50, 1994).
However, most semiconductor packages hitherto proposed are by no means those which can be adapted to the smaller size and higher integration, can be prevented from package cracking, have a good reliability and also have a good productivity.